| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 107 === With the advance of semiconductor technologies, the design of Very-Large-Scale Integration (VLSI) circuits becomes more complex. System-on-Chip (SOC) has become the main stream of VLSI design style . Because SOC designs usually contain both analog and digital circuits, it is important to have an Analog/Mixed-Signal (AMS) verification flow for chip development. In this thesis, we adopt Wave Digital Filter(WDF) theorem to map analog circuits into digital circuits for emulating analog circuits. This method uses incident and reflected waves to model circuit characteristics. Each analog component can be transformed into digital component in WDF framework to support the co-simulation with digital circuits.
Based on the previous studies for the simulation process of WDF architectures, this thesis presents an automatic environment for converting analog circuits into WDF structures. Using the sensitivity-based method, the change of γ value at each adaptor becomes a formula related to the input voltage, This approach successfully avoids long calculation time by replacing the look-up table and interpolation method. In order to minimize hardware resource, integer linear programming algorithm is used to obtain the minimum number of required adaptors, The affine arithmetic model is also applied to calculate the minimum bit length with certain precision. As shown in the experimental results combining the proposed methods, the generated WDF circuits are greatly improve in terms of speed and area. The automation environment also improves the convenience for users to do analog emulation
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