| Summary: | 博士 === 國立中央大學 === 電機工程學系 === 107 === This dissertation presents three main research works: 1. the design and implementation of high-throughput hardware-efficient MIMO detectors, 2. the imperfect channel state information (CSI) improvement and a processor design for QRD-based MIMO-OFDM precoding system, and 3. a high configurable generalized matrix decomposition processor (GMDP) design and implementation for MIMO precoding. In our first work, we proposed the layer-dependent K-best search algorithm to reduce MIMO detector complexity with reasonable bit error rate (BER) performance. We also proposed a hardware-efficient high-throughput K-best search hardware architecture based on on-demand expansion (ODE) algorithm. Our proposed MIMO detector architecture based on the layer-dependent K-best algorithm and the proposed ODE architecture achieves the MIMO detection rate - 1 MIMO detection result per clock cycle. Based on the proposed architecture, one 4 × 4 detector IC was manufactured and measured. According to the measurement results, it reaches 4.08 Gbps throughput and a 17.6 Mbps/kilogates normalized hardware efficiency (NHE). The intra-layer folding scheme is proposed to trade enough throughput for lower hardware complexity for designing the 8 × 8 detector. Its post-layout simulation result offers 4.37 Gbps throughput and a 1713 Mbps/mm2 NHE. Compared with the conventional K-best MIMO detectors and some previous works, our designs are power-efficient and hardware-efficient. In addition, the scalability of the proposed 8 × 8 MIMO detector architecture is analyzed according to the number of antennas, constellation size, and K values, and the related throughput and gate count are investigated.
In our second work, we first analyze one kind of imperfect CSI, channel estimation noise, impact on QRD-based MIMO-OFDM precoding systems. Based on the noise reduction in sounding phase by the channel estimation filtering scheme – SndChFilt, we analyze and show the difficulties to do beamforming channel estimation filtering - the BeamChFilt scheme. Then, we propose other two beamforming channel estimation noise reduction schemes, BeamChEqual and BeamChReal for equal rate (ER)-QRD MIMO-OFDM precoding systems. BeamChEqual scheme reduces noise in CSI by the equal channel gain property of ER-QRD beamforming effective channel matrixes. BeamChReal scheme reduces noise by the real-valued channel gain property. Both schemes consume low computational complexity, require no extra communication protocol overhead, and are compatible with the IEEE 802.11 beamforming packet format. The proposed precoding scheme; ER-sorted QRD-TH (Tomlinson-Harashima) precoding with BeamChEqual, BeamChReal, together with SndChFilt; achieves approximate 4 dB SNR (signal to noise ratio) improvement in 1 or 2-user 8 × 8 precoding BER simulations. The pros and cons comparisons between the proposed ER-SQRD-THP, AMBER-SVD precoding, and GMD-THP are studied. Simulations show the ER-SQRD-THP with the proposed CSI improvement schemes achieves a good BER performance. We propose a processor architecture with those CSI improvement schemes. Finally, the CSI feedback with filtering hardware design considerations are analyzed.
In our third work, we propose an improved generalized matrix decomposition processor (GMDP). It supports computations of four kinds of 4 × 4 complex matrix decomposition algorithms, QR decomposition (QRD), singular value decomposition (SVD), eigenvalue decomposition (EVD), and geometric mean decomposition (GMD), using an array of 16 configurable processing elements and memory-based architecture. Each processing element contains one CORDIC for obtaining decomposition value and basis matrixes. The basis matrixes are computed by inverses of operations on the value matrix at the same time as the value matrix. In the improved architecture, each CORDIC is customized by all used operations. Our GMDP implementation achieves throughputs of 9.47M, 0.94M, 0.88M, 2.8M matrixes per second for 4 × 4 complex QRD, EVD, SVD, and GMD, respectively. The CORDIC-customized architecture saves a 12% gate count. In summary, this dissertation presents designs of three high quality processors for MIMO-OFDM systems: a high throughput MIMO detection processor, a CSI quality improvement processor for MIMO-OFDM precoding, and a high configurable generalized matrix decomposition processor.
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