Improvement of Solder Cap Deformation in Flip-Chip Packaging Process

• Main Authors: Lin, Chang-Hua-Chen, 林張華貞
• Other Authors: Pan, Fu-Ming
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/r9328h

碩士 === 國立交通大學 === 工學院半導體材料與製程設備學程 === 107 === To optimize operation performance and improve heat dissipation, more and more high performance integrated circuit (IC) chips are fabricated with flip chip land grid array (FCLGA) packaging technology. FCLGA without solder balls is usually designed to have exposed metal pads on the bottom of the packaging substrate, which can enhance heat dissipation to the printed circuit board (PCB) during IC operation. The FCLGA design has many merits desirable for advanced packaging, such as small size and light weight. For example, FCLGA with coreless substrate has been widely implemented to meet the trend of small dimension of package. However, stress may develop in the FCLGA package inducing a large strain on the substrate and thus causing package failure, such as necking and over-compression on the solder cap of copper pillar bumps and cracking around the solder cap area. In this study, we tried to improve the packaging process to minimize deformation failures of solder caps in the FCLGA package. The study focused on the optimization of the following process parameters to improve the production yield: underfilling under the chip, size increase of the solder mask between the two metal pads, modification of the molding compound process and changing the chip location on the substrate. The study shows that, when the chip is located at the center of the substrate, increasing the size of the solder mask produces a better improvement on the yield.However, solder cap deformation and substrate warpage are still significant. On the other hand, relocating the chip to the position right above one metal pad results in the best yield without modifying any packaging process parameter. According to the study, optimization of the substrate design and packaging processes can greatly improve the production yield as a result of minimization of deformation of solder caps and warpage of the substrate.