A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response

碩士 === 國立交通大學 === 電控工程研究所 === 107 === Advanced CMOS devices below 28nm allow supply voltages lower than 1V. For applications with higher input voltage (VIN) in such devices, stacked MOSFET structures with a three-level (3L) technology are commonly employed. The stacked structure can also reduce the...

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Main Authors: Chu, Li-Cheng, 朱立程
Other Authors: Chen, Ke-Horng
Format: Others
Language:en_US
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/7zpm8m
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spelling ndltd-TW-107NCTU54490172019-05-16T01:40:47Z http://ndltd.ncl.edu.tw/handle/7zpm8m A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response 帶有可調式電容技術的低輸出漣波和快速暫態響應 三級單電感三輸出電壓轉換器 Chu, Li-Cheng 朱立程 碩士 國立交通大學 電控工程研究所 107 Advanced CMOS devices below 28nm allow supply voltages lower than 1V. For applications with higher input voltage (VIN) in such devices, stacked MOSFET structures with a three-level (3L) technology are commonly employed. The stacked structure can also reduce the output voltage ripple substantially. The three-level topology applies three different voltages, VIN, 1/2VIN, and VSS, to the node VX. The operation mode is determined by the duty cycle (D), i.e., the node VX swings between 1/2VIN and VSS when D < 0.5, and between 1/2VIN and VIN, otherwise (D>0.5). Compare to the conventional two-level converter, the voltage swinging range of node VX is halved, leading to the reduction of the output voltage ripple. The thesis proposed a three-level single-inductor triple-output (SITO) converter and also compares the transient response with the SITO converter without the three-level technique. In state-of-the-art, the key issue of the three-level topology is how to calibrate the cross voltage of flying capacitor CFLY at the point of 1/2Vin. In general, the restrained output voltage ripple and the flatter inductor current (IL) slope seriously result in worse transient response and severe cross regulation (CR) problems, respectively. The analysis in the thesis shows that the three-level SITO converter achieves a smaller output voltage ripple in steady state, but it causes the problems of slower transient response time, longer recovery time, larger overshoot/undershoot, and severe CR. Thus, it is desired to develop a technique that can adjust the cross voltage of CFLY such that the three-level topology achieves higher efficiency, lower output voltage ripple, and fast transient response simultaneously. Chen, Ke-Horng 陳科宏 2018 學位論文 ; thesis 42 en_US
collection NDLTD
language en_US
format Others
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description 碩士 === 國立交通大學 === 電控工程研究所 === 107 === Advanced CMOS devices below 28nm allow supply voltages lower than 1V. For applications with higher input voltage (VIN) in such devices, stacked MOSFET structures with a three-level (3L) technology are commonly employed. The stacked structure can also reduce the output voltage ripple substantially. The three-level topology applies three different voltages, VIN, 1/2VIN, and VSS, to the node VX. The operation mode is determined by the duty cycle (D), i.e., the node VX swings between 1/2VIN and VSS when D < 0.5, and between 1/2VIN and VIN, otherwise (D>0.5). Compare to the conventional two-level converter, the voltage swinging range of node VX is halved, leading to the reduction of the output voltage ripple. The thesis proposed a three-level single-inductor triple-output (SITO) converter and also compares the transient response with the SITO converter without the three-level technique. In state-of-the-art, the key issue of the three-level topology is how to calibrate the cross voltage of flying capacitor CFLY at the point of 1/2Vin. In general, the restrained output voltage ripple and the flatter inductor current (IL) slope seriously result in worse transient response and severe cross regulation (CR) problems, respectively. The analysis in the thesis shows that the three-level SITO converter achieves a smaller output voltage ripple in steady state, but it causes the problems of slower transient response time, longer recovery time, larger overshoot/undershoot, and severe CR. Thus, it is desired to develop a technique that can adjust the cross voltage of CFLY such that the three-level topology achieves higher efficiency, lower output voltage ripple, and fast transient response simultaneously.
author2 Chen, Ke-Horng
author_facet Chen, Ke-Horng
Chu, Li-Cheng
朱立程
author Chu, Li-Cheng
朱立程
spellingShingle Chu, Li-Cheng
朱立程
A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response
author_sort Chu, Li-Cheng
title A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response
title_short A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response
title_full A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response
title_fullStr A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response
title_full_unstemmed A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response
title_sort three-level single-inductor triple-output converter with an adjustable flying-capacitor technique for low output ripple and fast transient response
publishDate 2018
url http://ndltd.ncl.edu.tw/handle/7zpm8m
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