0.8V Sub-mW 433MHz-band Transmitter and Receiver in 0.18μm CMOS

• Main Authors: Chen, Yen-Ting, 陳晏廷
• Other Authors: Liao, Yu-Te
• Format: Others
• Language: en_US
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/7a29z7

碩士 === 國立交通大學 === 電機工程學系 === 107 === Nowadays, with the development of silicon technology, the low-power system has become more and more popular in portable consumer electronics, bio-sensing systems, and internet-of-things applications. For these applications, there are three issues: the cost of the components, transmission distance, and battery life. The cost is determined with the number of the off-chip components and the size of each chip. The lower the number of the components and the chip size, the lower the price of the system; transmission distance is determined by the output power of the transmitter and the sensitivity of the receiver. To extend the distance, the output power and sensitivity should be higher, but this also causes an increase in power consumption; the system power consumption limits the battery life. In the thesis, a low-power 433MHz transmitter and receiver are proposed. To implement a low-power but high-accuracy transmitter, the work adopts a two-step frequency multiplication technique with the subharmonically injection-locked PLL (SILPLL) and the capacitive coupling circuit. The two-step frequency multiplication technique alleviates the high-power and noise problems that conventional high-order PLL suffers and balances the power consumption and noise performance. The chip was fabricated in a 0.18μm CMOS process, and the chip area is 2.23mm2. The output frequency of the PLL is 48MHz, and the phase noise is -95.42dBc/Hz @100kHz and -118.58dBc/Hz @1MHz. The system power consumption and output power is 248μW and -24dBm under 0.8V supply voltage, respectively. To obviate the requirement of the bulky SAW filter and crystal oscillator but still maintain high-sensitivity, the proposed low-power receiver adopts the mixer-first architecture to implement a high-Q channel selection, the frequency calibration path to optimized IF bandwidth and the VCO frequency, and the chopper amplifier to remove the effects of the flicker noise. The chip was fabricated with 0.18um CMOS process, and the chip area is 3.82mm2. The system power consumption and maximum data rate are 162μW and 30kbps under a 0.8V supply.