A Seventh-Order Low-Noise Discrete-Time Delta-Sigma Modulator for Audio Applications

• Main Authors: Chang, Shing-Yun, 張馨云
• Other Authors: Hung, Chung-Chih
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/n82kac

碩士 === 國立交通大學 === 電機工程學系 === 107 === Due to our ears’ high ability of sound distinction, the resolution demand of the audio applications is higher and higher, such as audio equipment or speech recognition. To obtain a well performed SNR, we usually use the delta-sigma modulator to implement the ADC. When the order of the system is higher, the ability of de-noise is stronger. However, it will be more unstable as the order gets higher, so most people choose the third-order system to avoid this problem. Thus, the goal of this research is to achieve a very low noise floor (in-band noise power) with a seventh-order delta-sigma modulator and still stay stable. In this thesis, the design of the seventh-order delta-sigma modulator will be presented. It is utilized as the ADC in the analog front end of MEMS microphones. The design has to be medium-low power, low frequency, high SNR, and low noise to fit the demand of hearing applications. Results show for a 24kHz signal bandwidth the ADC achieves a dynamic range of 79dB, a peak signal-to-noise and distortion ratio of 68.1dB, and a in-band noise of -90.2dBFS with an oversampling ratio of 32 (sample rate of 1.536MHz). It was fabricated in a TSMC 0.18-m CMOS process with a 2.306mm2 active area, and dissipates 7.5mW from a 1.8-V power supply.