| Summary: | 博士 === 國立交通大學 === 電子研究所 === 107 === While the manufacture process of InxGa1-xAs metal oxide semiconductor field effect transistors (MOSFETs) to address the leakage current issues for low power logic applications has been extensively investigated, fabrication process development for InAs channel high electron mobility transistors (HEMTs) is relatively unexplored.
Without the introduction of high-k dielectric materials, this dissertation studies advanced process technology development of InAs channel HEMTs for high speed and low power logic applications.
The dissertation is divided into four parts: (i) non-alloyed ohmic metal replacement, (ii) mesa sidewall channel etch, (iii) source connected field plate and (iv) tri-gate MESA techniques on InAs HEMTs. These four manufacture process techniques are categorized and quantified in order to ascertain the effects on InAs HEMTs performance improvement and the qualities by which they are evaluated.
These results indicate that: (i) although non-alloyed ohmic metal shows a little bit higher contact resistivity than alloyed ohmic contact, it does much improve the drain induced barrier lowering (DIBL) as compared with the device with alloyed ohmic metal, (ii) using the mesa sidewall channel etch process not only addresses the large gate leakage issue but also improves the subthreshold characteristics, (iii) applying source connected field technique on InAs HEMTs further improves the gate leakage current, subthreshold characteristics and achieves a high off-state breakdown voltage, and (iv) the designed tri-gate MESA InAs HEMTs structures which connects the Schottky layer and buffer layer simultaneously demonstrates better subthreshold swing, lower off-state current, and higher ION/IOFF ratio.
These findings have implications that InAs HEMTs could be potential devices for future high speed and low power logic applications in the post CMOS era.
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