| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 107 === This thesis mainly developed a multivariable analysis to study the source/drain(S/D) variation in FinFETs. With the scaling of CMOS technology, aggressive scaling of fin-pitch and contact length reduces the contact area. Nevertheless, few studies have been focused on the variation of S/D region, which should be a big concern for next generation device design. Then, we utilized the result of multivariable analysis to construct the Physical Unconable Function (PUF) and True Random Number Generator (TRNG). In the Internet of Things (IoT) era, both PUF and TRNG play very important role in embedded cryptographic system designs.
First, we developed a multivariable analysis to quantify the impact of S/D region variation on device driving current. When channel length scales down to nanometer, the channel resistance rolls off at the same time; however, Rsd accounts for an increasing proportion of the total resistance. Therefore, Rsd cannot be ignored while improving the performance of the advanced generation devices.
Next, to get more information about the Rsd, the Virtual Source Model will be introduced in chapter 2. Also, the doping profile along the direction of channel to S/D region can be extracted by discrete dopant profiling. Owing to these aforementioned techniques, the source of Rsd variation can be delineated, in which dopant is dominant (76.3~89.4%) and interface trap is a secondary factor (10.6~23.7%) with less contribution to the Rsd variation, in both n-FinFET and p-FinFET.
The Physical Unclonable Function (PUF) will be introduced in chapter 3. During IC manufacturing process, variability occurs and creates different physical microstructures. These manufacturing variations cannot be fully controlled and re-fabricated intentionally, so the underlying physical properties are unique and become silicon fingerprints of individual ICs. That’s why PUF can be seen as the fingerprint of devices; hence, the suitable variation source for PUF is important. We utilize the S/D mismatch current to achieve PUFs and show the great performance (Inter-HD~49.9952%, Hamming Weight~50%) of S/D-mismatch-based PUF. Also, after 150℃ 720hrs thermal stress experiment, the unstable bits are still near 0.
In the fabrication process, there are some lithography induced traps in S/D junction. These traps will induce not only the variation of S/D resistance, but also the RTN phenomenon. Because of the characteristic of randomness in RTN, we can use the junction-RTN phenomenon to construct the TRNG. In order to prove the randomness of TRNGs, we use the junction-RTN TRNG to generate 65536 random bits and evaluate these random numbers though NIST, showing that the random numbers pass 9 statistic tests.
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