| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 107 === In communication systems, most of data is performed in the digital domain, but the signal was transmitted in the analog domain. Therefore, the digital-to-analog converters are unavoidable. Data converters'performance is very important to signal quality. As the result, wide-band and high-dynamic-range converters is inevitable.
This thesis submits an 8-bit 10GS/s digital-to-analog converters, it was fabricated in a 28nm CMOS technology. The current-steering structure has been widely used in high-speed DACs, because the structure's speed is limited by output node. However, the non-ideal switching limits the bandwidth of spurious-free dynamic range (SFDR). The SFDR decreases when increasing input frequency.
For current-steering digital-to analog converter,current sources with high accurate are very important.Current sources with high matching property are required and penalty is large area,parasitic capacitor loading also degrade the signal bandwidth.The way to reduce loading is using compact current cells,but the compact ones have larger mismatching property.Therefore,we need to trade-off between high matching property and low parasitic capacitor loading.
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