A Novel Partition-Based Cell Generation for High Performance and Printability in Advanced Node

• Main Authors: Chang, Yao-Lin, 張曜麟
• Other Authors: Chen, Hung-Ming
• Format: Others
• Language: en_US
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/r3ymp7

碩士 === 國立交通大學 === 電子研究所 === 107 === As the complexity of a layout design grows, layout automation problem has been more and more important. Among all the solutions, The 1-D GDR layout style is the key to simplify the process and obtain high performance in a lithography-friendly way. In consideration of gate matching, transistor folding, area, wire length and stage-like line end gap, we present an effi cient and deterministic algorithm to generate 1-D layout in standard cells and memory cells. This algorithm features bi-partition tree and the selective stage. With bi-partition tree, we speed up the algorithm and guarantee the safety of the process. With objective functions in placement selection stage and routing stage, a lithography- friendly layout with low congestion, minimum area and high performance is proved to be generated.