The Process Development of a Heterogeneous InGaAs n-MOSFET Device with High Energy Gap InAlAs Back Barrier Layer

• Main Authors: Chen, Kai-Chun, 陳凱鈞
• Other Authors: Lin, Chun-Ting
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/8pwe5p

碩士 === 國立交通大學 === 照明與能源光電研究所 === 107 === In order to improve the performance of III-V MOSFETs and suppress the leakage current, we have adopted a layer of Indium aluminum arsenide (InAlAs) as a back barrier layer in the device structure. A mesa structure is also applied to improve the isolation between devices. Various process modules were developed and verified for InGaAs MOSFET integration. Besides, a novel T-gate formation method combing both anisotropic and lateral etching processes and a bilayer metal stack is proposed. For the MOS structure, HCl-based solution was used for surface clean before oxide deposition in order to improve the interface quality between Al2O3 and InGaAs. In terms of MOS characteristics, the measured maximum capacitance is 1.02 uF/cm2 (CET = 3.26 nm) with frequency dispersion of 3 %/decade and the extracted Dit is about 3E12 cm-2eV-1. TiN/Ti or Al/TiN/Ti-based metal contact structures were fabricated for InGaAs source/drain ohmic contacts, and the lowest contact resistance value of 1.39E-7 Ω•cm2 is achieved. Finally, the fabricated InGaAs MOSFET shows on-current Ion of 250 uA/um. However, the performance of devices in terms of on/off ratio and leakage level requires further improvement by material refinement as well as process optimization.