Making Aging Useful by Recycling Aging-Induced Clock Skew

• Main Authors: Tseng, Tien-Hung, 曾天鴻
• Other Authors: Wu, Kai-Chiang
• Format: Others
• Language: en_US
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/9797xu

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 107 === Device aging, which causes significant loss on circuit performance and lifetime, has been a primary factor in reliability degradation of nanoscale designs. In this paper, we propose to take advantage of aging-induced clock skews (i.e., make them useful for aging tolerance) by manipulating and recycling these time-varying skews to compensate for the performance degradation of logic networks. The goal is to assign achievable/reasonable aging-induced clock skews in a circuit, such that its effective performance degradation due to aging can be tolerated, that is, the lifespan can be maximized. On average, 25.04% aging tolerance can be achieved with insignificant design overhead. Moreover, we employ Vth assignment on clock buffers to further tolerate the aging-induced degradation of logic networks. When Vth assignment is applied on top of aforementioned aging manipulation, the average aging tolerance can be enhanced to 35.96%.