| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 107 === With the advance of technology nodes, complex and huge numbers of design rules are faced in integrated circuit (IC) physical designs under the considerations of design for manufacturability (DFM). Standard cells are the basic components of IC designs, and highly impact the quality of IC designs. With the evolution of PlanarFET structure technology nodes, the control of poly gate is reducing and the leakage is increasing. Given that issue, FinFET structure effectively increases the control of poly gate through three-dimensional structure, so the leakage issue can be solved. Therefore, the latest IC designs have used FinFET structure. In FinFET structure, middle of layer is the new material that can connect different structures, so there are major changes in design of standard cells. In this paper we propose a standard cell routing algorithm that is capable to flexibly assign routing source on FinFET structure routing layer for layout versus schematic (LVS) while considering complex design rules after transistor placement. The LVS and design rule check prevention determine whether the standard cell is success or not. We compare our result with the routing algorithm without using routing resource distribution in FinFET structure. The results show that the success rate of proposed routing algorithm achieve 25% more, and also reach 100% routing success rate in FinFET structure standard cell synthesis.
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