| Summary: | 碩士 === 華梵大學 === 電子工程學系碩士班 === 107 === The power loss has always been a problem that humans continue to explore, especially in this high-performance era. In which how to reduce the power loss of electronic products is an important issue. Improving power loss on power devices is a common goal for developers. In recent years, a new structure, called "Split-Gate Metal Oxide Semiconductor Field Effect Transistor (Split-Gate MOSFET)", has been developed, which power loss has been improved, and can be operated in high frequency environments. In this thesis, SILVACO simulation software was used to simulate a 100-volt Split-Gate MOSFET and to study its characteristics. The Split-Gate MOSFETs were optimized by simulation for the purpose of reducing their on-resistance. First the size of the Split-Gate MOSFET was scaled. The purpose is to reduce the specific on-resistance (Ron,sp). Finally, we changed the structure of the device and proposed the Multi-Split-Gate MOSFET including 2 Split-Gate, 4 Split-Gate and 6 Split-Gate. The characteristics of 4 Split-Gate is better than others. Therefore, this structure had been further optimized for the miniature size finally. After a series optimization, compared with 2.5 um cell pitch Split-Gate, Ron,sp had reduced about 55% for new structure with 2.0 um cell pitch and 4 Split-Gate in this paper.
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