| Summary: | 碩士 === 逢甲大學 === 電子工程學系 === 107 === The first part of this paper is mainly based on thin film transistors. The polycrystalline silicon thin film transistor (poly-Si TFT) has a higher electron mobility than the amorphous germanium film transistor, and thus is widely used in active-matrix liquid crystal displays (AMLCD).
The poly-Si TFT has high mobility and driving current compared with the amorphous silicon (a-Si) TFT. The conventional poly-Si TFT has a high electric field near the channel/drain junction. It is the major cause of impact ionization, which cause a serious kink effect.
Many structures have been reported to improve the high electric field near the channel/drain junction, such as offset-gate, raised source/drain (RSD), lightly Doped Drain (LDD), and gate-overlapped lightly doped drain (GOLDD). Although the high electric field can be effectively suppressed, the offset-gate and LDD device’s ON-current is significantly decreased because of an additional series resistance. In the past, the conventional TFT current was slightly insufficient.
If the double gate structure proposed in the past is used, the current value of the saturation region can be effectively increased. However, the double gate structure requires an additional mask to define the Bottom Gate, thus increasing the cost required for the process.
In this study, we have proposed a new process design method that uses a chemical mechanical polishing process to create a double gate structure that not only maintains the same four masks as the conventional single gate, but also has no problem with the upper and lower gates being inaccurate. It also reduces the ion implantation process, saving the cost of exposure and ion implantation. The double-gate (DG) design exhibits that the ON-current of proposal TFT is about twice higher than conventional TFT. Therefore, the proposed TFT can be a promising design for fully-integrated AMLCD for SOP high performance digital and analog circuit.
The second part of this paper is based on power device. In recent years, power MOS field-effect transistor (MOSFETs) have been widely used in many fields, including consumer electronics, computers, mobile phones, automotive electronics and home appliances. With the advancement and development of society, energy is fast. Consumption, how to use energy efficiently, and saving unnecessary energy expenditures are quite important issues in the future. Reducing the power loss of components has become the goal of component designers. For power metal oxide semiconductor field effect transistors (MOSFETs), the two most important characteristics are breakdown voltage (BV) and specific on-resistance (Ron,sp), but it is difficult to achieve both high (BV) and low (Ron,sp) at the same time. The parameters are related to each other. Ron,sp determines the power consumption of the device, so constant effort is required to develop a power MOSFET for a given fixed (BV) and reduce the (Ron,sp) value. A number of device concepts have been proposed to improve the balance between (Ron,sp) and (BV). The Spite gate UMOSFET split gate is also an alternative solution that reduces gate charge and capacitance, further reducing switching losses relative to Trench gate UMOSFET trench gates.
We propose a 150 V double-layer EPI UMOSFET (DEPISG). The DEPISG UMOSFET divides the epitaxial layer of the split gate into two layers. Because different doped epitaxial layers are used, different electric field peaks are generated in the drift region. Therefore, a higher breakdown voltage (BV) of the device and a lower resistance value in the drift region can be achieved, and a lower specific on-resistance is obtained.
In addition, we will use the ISE-TCAD simulation software to verify the component characteristics of the structure and verify the implementation.
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