| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 107 === This paper based on the most advanced SRAM 6T [2]it used (1) Dual-Split-Control Scheme (DSC) (2) Dynamic adjustment of auxiliary voltage(CVSS-assist voltage, VSSA) VSSA helping DSC6T to improved in Vmin Reduction (3) Charge-Shearing-Based CVSS Generation, CSVG in order to achieve low area cost and high speed operation at NVT .
Research found and confirmed that [2]DSC6T SRAM has following disadvantages : (1) CSVG scheme extremely complex and consumes area 、(2) VSSA voltage is susceptible to PVT variation (3) VSSA variation affects the lowest NVT’s Vmin 、(4) VSSA of the dynamic adjustment operation takes time and the high-speed operation target is greatly reduced.
Based on the above mentioned ; Retaining the small area of DSC6T and the advantage of applying read/write assist VSSA . The VSSA generating circuit with feedback control VSSA(Feedback VSSA Generator, FBVG) been proposed to achieve four major benefits. (1) Significantly reduce the assist circuit area、(2) Adaptability to reduce assist voltage variation、(3) Effectively reduce the minimum NVT voltage and (4) Achieve high-speed operation targets.
We not only proposed FBVG but also propose that the single-ended sense amplifier , DIO DASR solves the two major problem of original one . (1) The Vref generator is difficult to design to achieve the desired range. (2) DC power consumption when the Data line is turned on.
Two new circuit designs have been applied to 2KB SRAM designs in 28nm and 22nm CMOS two-generation processes. 22nm redesigned Vmin at 0.55V ,this paper proposed Vmin at 0.5V、2 times speed increased and deceased 3.2 times area .
Index terms: 6T SRAM, Dual-Split-Control Scheme , Assist Circuits, Low Power
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