Optimal IR-aware Routing Trees for Multiple Power Nets in Mixed-Signal Design

碩士 === 國立中正大學 === 電機工程研究所 === 107 === Due to the scaling down of the IC manufacturing technique, IR-drop has become a critical issue in modern mixed-signal SoC circuit design. When designing power delivery network (PDN), voltage drop between power supply and cell pins may cause performance degradati...

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Main Authors: WANG, WEI-DA, 王偉達
Other Authors: LIN, PO-HUNG
Format: Others
Language:en_US
Published: 2019
Online Access:http://ndltd.ncl.edu.tw/handle/zy75k7
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spelling ndltd-TW-107CCU004420742019-11-02T05:27:09Z http://ndltd.ncl.edu.tw/handle/zy75k7 Optimal IR-aware Routing Trees for Multiple Power Nets in Mixed-Signal Design 針對混合式訊號多電源網路之最佳壓降考慮繞線樹 WANG, WEI-DA 王偉達 碩士 國立中正大學 電機工程研究所 107 Due to the scaling down of the IC manufacturing technique, IR-drop has become a critical issue in modern mixed-signal SoC circuit design. When designing power delivery network (PDN), voltage drop between power supply and cell pins may cause performance degradation and functional failure. Although increasing wire width can decrease the IR-drop effect, it also increases the total metal usage at the same time, which may result in the waste of routing resource. The routing resource distribution among multiple nets is another challenging problem that need to be solved. In order to obtain optimal PDN with the least total metal usage while satisfying all IR-drop constraints, we propose an IR-aware routing tree generation method based on a multi-layer obstacle-avoiding rectilinear extending graph (ML-OAREG). The routing source distribution is also considered by adding additional congestion penalties in ML-OAREG. Experimental results show that our method can decrease average metal usage by around 34\% with more than 10X run time acceleration compared with the recent work. LIN, PO-HUNG 林柏宏 2019 學位論文 ; thesis 43 en_US
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language en_US
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description 碩士 === 國立中正大學 === 電機工程研究所 === 107 === Due to the scaling down of the IC manufacturing technique, IR-drop has become a critical issue in modern mixed-signal SoC circuit design. When designing power delivery network (PDN), voltage drop between power supply and cell pins may cause performance degradation and functional failure. Although increasing wire width can decrease the IR-drop effect, it also increases the total metal usage at the same time, which may result in the waste of routing resource. The routing resource distribution among multiple nets is another challenging problem that need to be solved. In order to obtain optimal PDN with the least total metal usage while satisfying all IR-drop constraints, we propose an IR-aware routing tree generation method based on a multi-layer obstacle-avoiding rectilinear extending graph (ML-OAREG). The routing source distribution is also considered by adding additional congestion penalties in ML-OAREG. Experimental results show that our method can decrease average metal usage by around 34\% with more than 10X run time acceleration compared with the recent work.
author2 LIN, PO-HUNG
author_facet LIN, PO-HUNG
WANG, WEI-DA
王偉達
author WANG, WEI-DA
王偉達
spellingShingle WANG, WEI-DA
王偉達
Optimal IR-aware Routing Trees for Multiple Power Nets in Mixed-Signal Design
author_sort WANG, WEI-DA
title Optimal IR-aware Routing Trees for Multiple Power Nets in Mixed-Signal Design
title_short Optimal IR-aware Routing Trees for Multiple Power Nets in Mixed-Signal Design
title_full Optimal IR-aware Routing Trees for Multiple Power Nets in Mixed-Signal Design
title_fullStr Optimal IR-aware Routing Trees for Multiple Power Nets in Mixed-Signal Design
title_full_unstemmed Optimal IR-aware Routing Trees for Multiple Power Nets in Mixed-Signal Design
title_sort optimal ir-aware routing trees for multiple power nets in mixed-signal design
publishDate 2019
url http://ndltd.ncl.edu.tw/handle/zy75k7
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