Optimal IR-aware Routing Trees for Multiple Power Nets in Mixed-Signal Design
碩士 === 國立中正大學 === 電機工程研究所 === 107 === Due to the scaling down of the IC manufacturing technique, IR-drop has become a critical issue in modern mixed-signal SoC circuit design. When designing power delivery network (PDN), voltage drop between power supply and cell pins may cause performance degradati...
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| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/zy75k7 |
| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 107 === Due to the scaling down of the IC manufacturing technique, IR-drop has become a critical issue in modern mixed-signal SoC circuit design. When designing power delivery network (PDN), voltage drop between power supply and cell pins may cause performance degradation and functional failure. Although increasing wire width can decrease the IR-drop effect, it also increases the total metal usage at the same time, which may result in the waste of routing resource. The routing resource distribution among multiple nets is another challenging problem that need to be solved. In order to obtain optimal PDN with the least total metal usage while satisfying all IR-drop constraints, we propose an IR-aware routing tree generation method based on a multi-layer obstacle-avoiding rectilinear extending graph (ML-OAREG). The routing source distribution is also considered by adding additional congestion penalties in ML-OAREG. Experimental results show that our method can decrease average metal usage by around 34\% with more than 10X run time acceleration compared with the recent work.
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