| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 107 === Traditional circuit design to consider that operations is correctly under all conditions, leading to excessive margin because worst case design, timing sensor and adaptive scaling technology is effective to reduce voltage and excessive margin, this paper us pre-error AVS control loop system, applied to deep neuron network to implement on 28nm FPGA, using delay distribution of 10,000 handwritten MNIST images and 10mv/step , Markov chain to estimate the AVS results. Deep neural network has fault tolerant to operation error data, when the data appeared a little error, system is still correct to working, Providing more margin than the general system, but MNIST pattern characteristic that adaptive voltage scaling need a very long cycle to adjust voltage, so we propose a new improvement strategy, response time to reduce 16.857 times, and support aggressive voltage scaling.
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