A Reduced Storage Row-Stationary CNN Accelerator Design With Low Wiring Complexity

• Main Authors: XU, XIAO-WEN, 徐孝文
• Other Authors: YEH, CHING-WEI
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/vsnp32

碩士 === 國立中正大學 === 電機工程研究所 === 107 === Ever since its publication in 2016 ISSCC, the Row Stationary (RS) architecture has been accredited for its high performance and low energy consumption in accelerating the computation of various CNN's. As such, follow-up research works has been sustaining momentum. In a recent subsequent study, the Row Stationary Plus (RS+) architecture was proposed to reduce the number of registers in RS, but it incurred wire delay problem in the layout stage. In this thesis, we propose a Hierarchical Row Stationary Plus (HRS+) architecture that utilizes a two-level hierarchy to mitigate the wiring problem while preserving the register advantage of the RS+ architecture. The HRS+ is compared to redesigned RS, RS+, and a recent CNN accelerator design called COSY. Experiment results show that the HRS+ compares favorably in terms of area and power consumption.