I/O Pin Design of Standard Cells for Sufficient Accessibility
碩士 === 元智大學 === 資訊工程學系 === 106 === This thesis investigates I/O pin accessibility problem of standard cells designed with a 15nm process technology defined in FreePDK15. We are interested in knowing how short an I/O pin will be so that good pin accessibility can still be achieved with shortest pin l...
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| Format: | Others |
| Language: | zh-TW |
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2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/uxep5h |
| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 106 === This thesis investigates I/O pin accessibility problem of standard cells designed with a 15nm process technology defined in FreePDK15. We are interested in knowing how short an I/O pin will be so that good pin accessibility can still be achieved with shortest pin length. To perform this research, the 15nm open cell library from NanGate and four of its variants with a reduced number of access points per pin are used/created for our study. The experimental results show that line-end rules on metal layers severely reduce pin accessibility. The results also show that a viable standard cell library should be formed only by the cells that have the number of access points per pin greater than two regardless of whether a detailed router uses M1 for routing or not. The methodology presented in this work though is illustrative based on FreePDK15, it can be generally applied to other process technologies. However, one may come to a conclusion different from that presented here.
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