A hardware design for converting the low dynamic range image to the high dynamic range image

• Main Authors: WU,CHIA-CHIN, 吳佳晉
• Other Authors: SHIAU, YEU-HORNG
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/5ym9hw

碩士 === 國立雲林科技大學 === 電機工程系 === 106 === LCDs(Liquid-crystal display) is truly an epoch-making product of the 20th century. The image resolution is from FULL HD to 4K, and the recently launched 8K TV. The depth of the image is also extended from the traditional 8-bit to 10-bit or even 12-bit. In addition, the most noticeable is that the brightness of the screen has also increased from the traditional hundreds of cd / m2 (candle / square meter) to thousands of cd / m2. This thesis proposes a conversion algorithm form low dynamic range image to high dynamic range image. This method can improve the image that can’t be perfectly rendered on high-order display to a more perfect high dynamic range image, and the image details are still preserved when the false contour phenomenon is eliminated. This method is mainly divided into two parts. In the first step, the image details are saved and the bilateral filter is used to reduce the false contour phenomenon. In the second step, we select the appropriate clipping point based on the image characteristics to enhance the brightness contrast with two different linear scaling functions and finally enhance the image edges. From the experimental results, it can be seen that compared with the simple linear scaling for bit width, the results can reduce the false contour phenomenon. The results also have better rendering effect in the high brightness area and keep the image details. Because restoring the scene brightness radiation map is consideration, the visual quality of the transformed image is closer to the reality. To achieve the requirement of real-time applications, we designed the hardware architecture of the proposed method. From the results, the quality of image can be compared with the software. The hardware also has a faster processing speed. The implemented results showed that the number of logic element is 8.2K and the working frequency can reach 100MHz.