Signal Integrity Improvement for Mobile Devices with M-PCIe Bus

• Main Authors: Tsung-Jen Chuang, 莊宗仁
• Other Authors: Kuang-Yow Lian
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/qj27ev

碩士 === 國立臺北科技大學 === 電機工程系 === 106 === After Intel Corporation published PCI (Peripheral Component Interconnect) as a standard of local computer bus in 1991, PCI Express was officially announced in 2002, which is also abbreviated as PCIe. It extends the concept of PCI architecture and communication standard but based on a faster serial communication system. When considering rapidly growing in the application of mobile products, it is inevitable to focus on power consumption and signal interference of high-density multi-layer traces. To this end, Intel evolved M-PCIe (Mobile PCIe) as an extended communication standard of PCI Express in 2012. This indicates that the interface signal improvement solutions used in PC (Personal Computer) is no longer suitable for current mobile products such as smart phones or tablet computers. This thesis first explains how M-PCIe dramatically save the power consumption according to the discussion of improvements such as M-PCIe Band Width and Clock Timing, the differences of M-PHY (Port Physical Layer) interface, variations in the link layer, and the mechanism changes of power management. Furthermore, as the purpose to meet the industry standard through Eye Diagram verification, a solution was presented to gradually improve the integrity of M-PCIe bus signal in the system. The solution includes the design correction on PCB layout, setting changes of bus parameters, and values replacement for peripheral passive components. The Eye Diagram displayed on oscilloscopes is the pattern of high-speed digital signals in the bus. It is an indicator to evaluate the performance of the circuit by analyzing the size of white eye in the Eye Diagram. The preliminary circuit design needs to be redesigned through the above three main steps if it failed to the Eye Diagram verification. The redesign was performed by gradually adjusting the parameters and the passive component values of the peripheral bus, whereas considering the changes in power consumption. Experiments were repeatedly carried out until to pass the Eye Diagram verification.