| Summary: | 碩士 === 聖約翰科技大學 === 電機工程系碩士在職專班 === 106 === This thesis focuses on the problems of increasing the efficiency of Chips Tests. This work also proposes a noble design of multiplier PCB Probe Card. First of all, matching to the parameters of restricted Testers and the specification of PCB Board Probe Card; subsequently, satisfactions on the range requirements of the effectives on Probe Card design; afterward, fitting the constant Board Thickness to increase the layers of Board Stack up; finally, employing the impedance control to develop the noble design of multiplier PCB Probe Card from 32 to 64 Pieces Board to increase efficiency of chips Tests. There are some merits of this design. The numbers of points as to Probe Card welding are increasing. Furthermore, the efficiency of Chips Tests is increasing as well. Numerous simulations are made to demonstrate the efficiency of this design.
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