Design and applications of improved Half HPL multilayers of High Aspect ratio PCB on Via plug Cantilever Probe Card

• Main Authors: TSENG, CHIA-MING, 曾嘉銘
• Other Authors: LIN, SHIEH-SHING
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/w6hqr5

碩士 === 聖約翰科技大學 === 電機工程系碩士在職專班 === 106 === This thesis focuses on the hitches of welding assembly as to the Cantilever Probe Card on no-plug hole PCB. This work also employs the corresponding technology of PCB Via plug process proposing a design of improved Half HPL multilayers of High Aspect ratio PCB on Via plug Cantilever Probe Card. There are some benefits on this improved design. 1 increasing the stability of Needles welding assembly of operators in wafers Tester side; 2 elimination the contamination problems of fluxes and solders between the Wafer side and Tester side while welding assembly; 3 upgrading the quality of chips capacitance though welding assembly in Tester side; 4 shortening the operating time of welding assembly; 5 easy to maintain. Numerous simulations have been made to demonstrate the stability of the proposed design. Keywords: Via plug, High Aspect ratio, PCB, Wafer side, Cantilever Probe Card