| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === Because the System-on-Chip (SoC) system has become more complicated than before, the need of large-capacity internal memory in SoCs is increasing. Therefore, SDRAM and its related controller are needed in SoCs . The architecture based on ARM architecture dominates the market. Hence, in this thesis, we design and implement an AMBA- AHB5-based dynamic memory controller.
The dynamic memory controller contains three parts: the AHB5 interface, controller, and physical layer. This controller has three important features. First, it provides a portable user access interface that can be easily integrated with compliant CPU. Second, a dual-clock-domain design allows the user to access the physical and memory controller in different clock domains. Third, a power-saving controller and a data burst controller are used to reach high performance and low power dissipation.
The design of memory controller is compliant to DDR4 SDRAM and AMBA AHB5’s specification. The resulting DDR4-SDRAM controller realized in Xilinx Virtex6 XC6VCX75T consumes 527 LUTs (Lookup Table). Its maximum operating frequency is 53.6 MHz in the controller and 200 MHz in the physical layer.
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