| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === Low power integrated circuit designs were introduced in this thesis. The goal is
to realize innovative RFIC design which can contribute in lowering power
consumption while maintain acceptable performance. There are three chip designs
proposed in this work namely “Low Phase-Noise Oscillator with Filter for Harmonic
Suppression”, “A Fully-Integrated 4mW Super-Regenerative Receiver (SRR) with
TSPC Divide-by-8 Frequency Divider”, and “A 1.1pJ/bit OOK Transceiver”.
The design of oscillator was presented in chapter 6. The proposed low power and
low phase-noise CMOS oscillator was designed using a parallel LC filter in shunt
with a differential high-pass filter for harmonic suppression. The proposed p-core
oscillator was fabricated in the TSMC 0.18μm SiGe BiCMOS technology, and the die
area is 1.163 × 1.149 mm2. At the power consumption of 1.53 mW, the phase noise is
-130.31dBc/Hz at 1 MHz offset frequency from the center frequency 2.32 GHz. The
figure of merit (FOM) is -195.77dBc/Hz. Chapter 7 presents a low power
super-regenerative receiver centered at 3.6 GHz. The receiver was designed in the
TSMC 0.18 μm CMOS process and consists of LNA, VCO, envelope detector and
divide-by-eight true-single phase clocking (TSPC) frequency divider. The effort to
replace conventional D Flip flop frequency divider by a TSPC based frequency
divider was done. TSPC promises minimum chip area and offers low power
consumption. Moreover, both LNA and VCO share the same inductor for smaller die
area. As a whole, the chip SRR consumes 4.01 mW at 1.5 V and achieved die area is
1.045 ×0.896 mm2. Lastly, a transceiver was introduced in chapter 8. The OOK
transceiver have chip area of 1.054 × 1.081 mm2. The chip was implemented in
TSMC 0.18 µm CMOS process technology and it can operate at 4GHz band.
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