Hardware/Software Codesign and Implementation of a Two-stage Block-based Algorithmic Processing System for Circular Hough Transform

• Main Authors: Yi-Wei Fang, 方毅瑋
• Other Authors: Chen-Mie Wu
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/472x5r

碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === This thesis is related to the hardware/software codesign and implementation of a two-stage block-based algorithmic processing system for the circular Hough transform. The related research work includes four parts: The first part is about the software design of a two-stage block-based circular Hough transform algorithm. After analyzing the property of the circular Hough transform algorithm and considering about the limited memory resources in the embedded systems, a two-stage block-based circular Hough transform algorithm has been developed. In this part, C language is used to write the program for verifying this proposed algorithm. The second part is to design and implement an algorithmic processor for the two-stage block-based circular Hough transform. The processor consists of a control unit, a source-data-buffer module, a coordinate-generator module, a votes-generator module, a voting module, and a local-max module. The custom hardware is integrated into a system on a programmable chip and implemented on the Altera FPGA development board. The third part is related to the implementation and verification of the hardware/software codesign for an algorithmic processing system. Here, with NIOS II IDE, driver and firmware programs are written to verify and analyze the functionality of the system. The fourth part is to evaluate the performance of the algorithmic processor. On the whole, the goal of this thesis is to do research on a two-stage block-based algorithm for the circular Hough transform and to design and implement an algorithmic processing system for it. Meanwhile, this algorithmic processing system has been implemented on an FPGA development board to compare and prove that the algorithm and hardware processor developed in this thesis have nice performance.