| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === This thesis focuses on researching and developing in timing skew calibration of high-speed time-interleaved (TI) ADCs. The operating speed of single-channel ADCs are limited by CMOS process technologies. When the sampling frequency cannot meet the increase in the linear relationship between power consumption and sampling frequencies, the time-interleaved operation can be used to achieve a low power demand. But the time-interleaved architecture derives the problem of inconsistent sampling times between channels, seriously affecting the performance of high-frequency input signals. Therefore, this paper presents a new clock skew correction technique to solve the problem of inconsistent sampling time between channels.
Compared with other clock skew correction schemes, this thesis proposed the clock skew correction technology. The hardware cost of the proposed skew calibration algorithm is lower than prior works. In the clock correction section, only an additional digital control delay circuit is required. In the clock skew detection section, the adder is used instead of the multiplier, which greatly reduces the complexity and design difficulty on the hardware. In the behavioral simulation and analysis (using MATLAB simulation), the feasibility of this algorithm has been verified. As a result, we have implemented an 8-bit 5-GS/s TI-ADC in a 55nm low-power CMOS process with a chip area of 4.84 square millimeters.
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