Model Establishment and Deep-Neural-Network Solutions for Signal Integrity in DDR Systems
博士 === 國立臺灣大學 === 電信工程學研究所 === 106 === The double data rate (DDR) memory system has been widely used in many electronic devices. As its data rate has reached the Gigabit range and many signal integrity (SI) problems arise in the signal lines. In this thesis, SI problems of three kinds of topologies...
Main Authors: | Kang-Yun Yang, 楊岡昀 |
---|---|
Other Authors: | Ruey-Beei Wu |
Format: | Others |
Language: | en_US |
Published: |
2018
|
Online Access: | http://ndltd.ncl.edu.tw/handle/kcmy8u |
Similar Items
-
Analysis and Design of Signal Integrity for DDR3 Memory System on Two-Layer PCB
by: Chang-Wei Lo, et al.
Published: (2014) -
A Statistical Analysis of Jitter Signal in DDR Memory
by: CHANG, NICHOLAS, et al.
Published: (2016) -
DDR-Geschichten
by: Manfred Aschke
Published: (2005-01-01) -
Why Human Papillomaviruses Activate the DNA Damage Response (DDR) and How Cellular and Viral Replication Persists in the Presence of DDR Signaling
by: Molly L. Bristol, et al.
Published: (2017-09-01) -
Signal and Power Integrity Co-Simulation and Analysis for DDR3 Memory on Industrial Platform PCBs
by: Yong-Lin Chen, et al.
Published: (2014)