| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === Sparse code multiple access (SCMA) is one of the most promising solutions among non-orthogonal multiple access (NOMA) technologies for the growing demand of massive machine type communications (mMTC), which is essential for the fifth-generation (5G) system. However, the complexity for SCMA detection is extremely high and no hardware implementation has been proposed in the open literature. In this thesis, a high-throughput, low-complexity minimum mean-square error with parallel interference cancellation (MMSE-PIC) detection for multiuser SCMA is proposed to reduce the computational complexity. A 96.3% complexity reduction is achieved for a 16QAM SCMA system with 8 frequency bands and 12 users (i.e., a 16QAM 8x12 SCMA system). The SCMA detector is reconfigurable to realize both the MMSE-PIC algorithm and MMSE-PIC-based message-passing algorithm (MPA). It is able to support both 4x6 and 8x12 SCMA systems with QPSK and 16QAM modulations. The proposed SCMA detector is integrated into a low-density parity-check (LDPC)-coded iterative detection and decoding (IDD) receiver. The interface between the SCMA detector and the LDPC decoder is properly designed to avoid data collision with a minimized latency and a 100% hardware utilization. The IDD receiver achieves a 3dB-gain compared to the non-IDD counterpart. Fabricated in a 40nm CMOS technology, the chip integrates 10.9M logic gates in area of 3.382x3.382mm2 and achieves a maximum throughput of 2.069 Gb/s. It dissipates 813mW at 200MHz from a 0.9V supply.
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