| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === In this thesis, high-linearity mixers with sliding-IF architecture including an IQ first stage up-conversion mixer and a second stage up-conversion mixer are proposed.
This thesis includes two works. The first work is an IF up-conversion mixer which converts the baseband signal to an IF frequency of 7.2 GHz. This work employs current-mirror technique to improve linearity. This work aims to reduce the non-linearity duo to cascaded structure. This circuit is fabricated in the TSMC 40-nm CMOS low power process. Measurement results have shown that conversion gain is 4.1 dB. Measured linearity of the OP1dB and OIP3 are -5.9 dBm and 4 dBm, respectively. With a 1.1-V supply voltage, the power consumption is measured to be 10.9 mW.
The second work is a RF up-conversion mixer which converts frequency from 7.2 GHz to 36 GHz. This work employs complementary transconductance linearization to improve linearity. This work aims to reduce the transistor nonlinearity in high frequency. This circuit is fabricated in the TSMC 40-nm CMOS low power process. Measurement results have shown that conversion gain is 1.5 dB. Measured linearity of the OP1dB and OIP3 are -6.7 dBm and 4.5 dBm, respectively. With a 1.1-V supply voltage, the power consumption is measured to be 5.7 mW.
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