Receiver Front-end Circuits for 5th Generation Mobile Communication System

• Main Authors: Pei-Yi Chen, 陳沛邑
• Other Authors: Tsung-Hsien Lin
• Format: Others
• Language: en_US
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/4ntwz6

碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === The goal of this research is to develop RF front-end circuits for 5th generation mobile communication system (5G). 5G is the extension of existing 4th generation mobile communication (4G) to provide higher data rate, lower latency and superior user experience. In respect to RF front-end design, the key technologies in 5G are (1) circuits operating at millimeter wave bands to provide larger data bandwidth (2) beamforming technique which utilizes multiple antennas to create a highly directional beam to compensate the path loss at millimeter wave frequencies. The main target of this research is to develop circuits which meet the system requirements in 5G. In Chapter 1, the system-level design considerations of the target transceiver are discussed. Basic characteristics and advantages of array transceiver are analyzed. Design considerations related to system architecture and link-budget are also presented. In this work, a low noise amplifier (LNA) and a downconverter are designed and implemented. In Chapter 2, the design of the LNA is discussed, including specifications, circuit architecture, analysis, design procedure and measurement result. The noise figure of the LNA is optimized based on the two-port noise theory. Two circuit techniques are used to improve the circuit linearity, and the corresponding mechanisms are analyzed. The designed LNA is implemented in TSMC 40 nm CMOS technology. It achieves 19 dB gain, 3.5 dB noise figure, -16 dBm P1dB and 20 mW power consumption. The design of the downconverter is discussed in Chapter 3, several popular downconverter circuit architectures are compared, and the architecture to meet the target requirement is proposed. The cross-coupled common-gate architecture is used to implement a high linearity and low power mixer input stage, which is necessary to satisfy the target system requirement. The designed downconverter is implemented in TSMC 90 nm CMOS technology. It achieves 5.2 dB voltage conversion gain, -2.5 dB power conversion gain, 15.2 dB noise figure, -6 dBm IP1dB. The mixer core consumes 5 mW and total power consumption (include buffer) is 20 mW. In Chapter 4, the conclusion and future work of this research are summarized.