| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === Channel equalization and digital predistortion (DPD) play important roles at the receiver and transmitter in communication systems. Since the advance of semiconductor technology, chips require higher bandwidth and transmission speed during serdes design of chip-to-chip wired communication in backplane for the sake of keeping abreast of high-performance calculation and high-density storage. However, the copper wire in the backplane exists distortions such as inter-symbol interference (ISI), which severely interferes the transmitted signals and causes performance degradation. Conventionally, the serdes design includes the equalizer to eliminate the impairments, and a decision feedback equalizer (DFE) is an ideal candidate to effectively suppress the ISI after trade-off performance, cost, and latency issues. Even if DFE is an efficient scheme, its architecture suffers from challenges of unfolding the feedback loop, when increasing the transmission rate in the next generation 56Gbps serdes design standards (IEEE 802.3BS) in wired communication systems. Therefore, in this thesis, we focus on how to design a parallel (N-way) architecture of DFE for high-speed application while maintaining effective performance of eliminating ISI distortion.
Besides, the power amplifier also induces nonlinear distortion at the transmitter and DPD is essential in transmitter design to eliminate the distortion. For the purpose of low-power saving design, the smaller back-off range is applied, which causes severe nonlinear distortion when signals operate in compressed region of power amplifier. However, traditional methods of DPD are hard to combat with severe nonlinear distortions and result in considerable performance degradation. Thanks to the evolutionary development in the fields of machine learning, many arts of neural network (NN) based DPD have developed. While the NN-based model provides good performance in power amplifier DPD, this model requires considerable time for training to reach convergence. Therefore, in this thesis, a low training overhead NN-based DPD with transformer layer architecture (TLA) is introduced, which reduce the training time while maintaining good error performance.
In this thesis, we first introduce conventional methods of ISI equalization and analyze the trade-off. Next, through loop-unrolling techniques and simplifying the algorithm of feed-forward filter (FFF), we can design a parallel and low-complexity architecture of DFE for high-speed demands. Based on adding TLA to conventional NN-based DPD, we further propose a low training overhead architecture. Finally, we conclude the research and possible future work.
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