Design of High-PSRR CMOS Impedance Measurement IC based on Coherent Technique

碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === A new measurement technique for impedance measurement analyzer is presented in this thesis to solve problems in the tradition measurement technique. In daily life, the impedance measurement analyzer is commonly used in biomedical applications, such as the body...

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Bibliographic Details
Main Authors: Chia-Wei Kuo, 郭家維
Other Authors: Liang-Hung Lu
Format: Others
Language:en_US
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/ns674t
Description
Summary:碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === A new measurement technique for impedance measurement analyzer is presented in this thesis to solve problems in the tradition measurement technique. In daily life, the impedance measurement analyzer is commonly used in biomedical applications, such as the body fat monitor, the cancer cell detection…etc. In other substances, the impedance changes when the state changes; for example, the corruption of foods, the liquid concentration...etc. To observe the changes in the materials more conveniently using the impedance measurement, the research needs to fabricate the large-sized and high-power traditional impedance measurement analyzer on an IC which is charged wirelessly. The range of measurement frequencies, the range of the device under test (DUT) impedance magnitudes and phases, noises, linearity…etc. are all needed to be considered for different applications. In order to work under wireless charging, the PSRR is an important consideration in the circuit. The ripple form the wireless power charging needed to be prevented. The coherent technique in impedance measurement analyzer is presented in this thesis. The PSRR of the magnitude measurement part’s output is improved. The thesis also uses the coherent technique so that the output of the phase measurement is not affected by measurement frequencies. The impedance measurement analyzer is fabricated in the 0.18-um CMOS process. To decrease the measurement error, we choose the magnitude and phase method for circuit architecture. Considering the low power consumption design, the integrator-based is used for phase measurement. The DC supply of chip is 1.8V. The power of chip is 2.52mW. The error of magnitude measurement is +0.89%/-0.58%. The error of phase measurement is +0.518°/-0.656°