A Systematic Design Methodology of Low-Power Time-Interleaved SAR ADC
碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === Successive approximation register analog-to-digital converters (SAR ADCs) are widely used in portable biomedical electronic systems due to their excellent power efficiency. However, the design optimization of SAR ADCs is often very time-consuming for many circu...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/286u3w |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === Successive approximation register analog-to-digital converters (SAR ADCs) are widely used in portable biomedical electronic systems due to their excellent power efficiency. However, the design optimization of SAR ADCs is often very time-consuming for many circuit engineers. This paper proposes a systematic design methodology for low-power time-interleaved SAR ADCs based on circuit behavioral model, aiming to assist engineers to evaluate the feasibility of a given specification of SAR ADC. The circuit behavioral model is based on MATLAB and consisted of mismatch model, delay model and noise model. The behavioral model is verified through transistor-level simulation with Cadence Spectre. Design examples based on 0.18um CMOS technology are also provided to demonstrate the accuracy of this design methodology.
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