Semi-Formal ECO Method
碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === Engineering change order (ECO) is a popular technique for rectifying design errors and specification changes in late design stages. We present a two-phase semi-formal patch generation to rectify multiple errors. We first 1) discover the functional matches in tw...
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| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/g3b8pj |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === Engineering change order (ECO) is a popular technique for rectifying design errors and specification changes in late design stages. We present a two-phase semi-formal patch generation to rectify multiple errors. We first 1) discover the functional matches in two circuits, then 2) optimize and generate a patch circuit from the matches. The ECO engine in this thesis discovers functional and structural matches in two circuits by the FRAIG technique and the simulation-guided cut-matching algorithm. Then, the combinational equivalence checking technique combined with a linear-time selection heuristic is processed to minimize the patch size from the matches. The experimental results show that this ECO engine can rectify circuits with small patch size within reasonable runtime.
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