Digital-to-Time Converter Based Phase-Locked Loop and Frequency Divider Design for Wireline and Wireless Applications

• Main Authors: Tun-Ju Wang, 王敦儒
• Other Authors: Tsung-Hsien Lin
• Format: Others
• Language: en_US
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/2uw428

碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === Digital-to-Time converters (DTC) have been widely used and it serves as one of the building blocks in many timing applications, such as the fractional-N PLL. The delay is of a DTC is controlled by a digital code, and the amount of delay is usually varied by switching on/off of a set of discrete elements, such as unit delay cells or charging capacitors. This thesis focuses on the applications of DTC. This thesis includes two works. The first work is “A 1.5-GHz Sub-Sampling Fractional-N PLL for Spread-Spectrum Clock Generator”. This work employs a fractional-N sub-sampling PLL, and supports spread-spectrum clocking. This work aims to reduce the electromagnetic interference (EMI) of a clock generator with its neighboring devices. It is fabricated in TSMC 180-nm CMOS process. Measurement results have shown that the EMI reduction with spread-spectrum clocking enabled is 18.98 dB. Measured RMS jitter of the output signal is 0.88 ps. With a 1.8-V supply voltage, the power consumption is measured to be 11.1 mW. The second work is “A 0.635~162.5 MHz Multiple Output Fractional Divider Using Phase Rotating Technique”. This work is realized by phase rotating technique, supporting multiple frequency outputs, with output frequency range of 0.635-162.5 MHz. This work aims to reduce the number of clock generators in a single SoC. It is fabricated in TSMC 90-nm CMOS process. Measurement results show that the proposed fractional divider functions properly under both integer and fractional division. Furthermore, this work supports dual outputs with two different division ratios, realizing a single input, multiple outputs frequency divider.