A 8~12Gb/s Full-Rate CDR with Continuous-Time Linear Equalization and Deserializer

碩士 === 國立清華大學 === 電機工程學系所 === 106 === With the advancement of technology, people are demanding the amount of data transmission. Therefore, we hope that the transmission speed can be increased significantly. And the parallel output will cause problems such as electromagnetic interference and crosstal...

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Main Authors: Yang, Zong-Han, 楊宗翰
Other Authors: Chu, Ta-Shun
Format: Others
Language:zh-TW
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/t3z3ky
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spelling ndltd-TW-106NTHU54411312019-05-16T01:08:03Z http://ndltd.ncl.edu.tw/handle/t3z3ky A 8~12Gb/s Full-Rate CDR with Continuous-Time Linear Equalization and Deserializer 具連續時間線性等化器及解串器的8~12Gb/s 時脈資料回復 Yang, Zong-Han 楊宗翰 碩士 國立清華大學 電機工程學系所 106 With the advancement of technology, people are demanding the amount of data transmission. Therefore, we hope that the transmission speed can be increased significantly. And the parallel output will cause problems such as electromagnetic interference and crosstalk. It will also cause problems on the circuit boards. Windings are more complicated, so serializer plays a very important role in many applications. With such high-frequency operation, the attenuation of the channel is very large, and serious inter-symbol interference may also occur, which causes the transmitted bits to interfere with each other and cause the eye amplitude on the eye diagram to become smaller or even disappear. Therefore, the bit error occurs dramatically. In order to suppress the electromagnetic interference, the transmitter often uses spread spectrum clocking to disperse the energy of the center frequency, and the high-frequency harmonics are also dispersed, which can reduce the interference to other signals. In order to solve the problem of attenuation of the channel above-mentioned, we must add an equalizer for compensation in front of the receiver, so that the attenuated signal can be reconstructed, and the open-eye state appears on the eye diagram, thus the clock and data recovery circuit works at the back. The original signal can be correctly judged to generate the correct clock to recover the received data. The equalizer must has self-adjustment function according to the environment, because different lengths of channel will have different attenuations. The purpose of this thesis is to make equalizer adaptable while using the PCIE 3.0 (5 inch) channel. And recovery the data transmitted by spread spectrum clocking by the clock data recovery. Then the serial data is recover to the parallel data by the deserializer. Chu, Ta-Shun 朱大舜 2018 學位論文 ; thesis 54 zh-TW
collection NDLTD
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description 碩士 === 國立清華大學 === 電機工程學系所 === 106 === With the advancement of technology, people are demanding the amount of data transmission. Therefore, we hope that the transmission speed can be increased significantly. And the parallel output will cause problems such as electromagnetic interference and crosstalk. It will also cause problems on the circuit boards. Windings are more complicated, so serializer plays a very important role in many applications. With such high-frequency operation, the attenuation of the channel is very large, and serious inter-symbol interference may also occur, which causes the transmitted bits to interfere with each other and cause the eye amplitude on the eye diagram to become smaller or even disappear. Therefore, the bit error occurs dramatically. In order to suppress the electromagnetic interference, the transmitter often uses spread spectrum clocking to disperse the energy of the center frequency, and the high-frequency harmonics are also dispersed, which can reduce the interference to other signals. In order to solve the problem of attenuation of the channel above-mentioned, we must add an equalizer for compensation in front of the receiver, so that the attenuated signal can be reconstructed, and the open-eye state appears on the eye diagram, thus the clock and data recovery circuit works at the back. The original signal can be correctly judged to generate the correct clock to recover the received data. The equalizer must has self-adjustment function according to the environment, because different lengths of channel will have different attenuations. The purpose of this thesis is to make equalizer adaptable while using the PCIE 3.0 (5 inch) channel. And recovery the data transmitted by spread spectrum clocking by the clock data recovery. Then the serial data is recover to the parallel data by the deserializer.
author2 Chu, Ta-Shun
author_facet Chu, Ta-Shun
Yang, Zong-Han
楊宗翰
author Yang, Zong-Han
楊宗翰
spellingShingle Yang, Zong-Han
楊宗翰
A 8~12Gb/s Full-Rate CDR with Continuous-Time Linear Equalization and Deserializer
author_sort Yang, Zong-Han
title A 8~12Gb/s Full-Rate CDR with Continuous-Time Linear Equalization and Deserializer
title_short A 8~12Gb/s Full-Rate CDR with Continuous-Time Linear Equalization and Deserializer
title_full A 8~12Gb/s Full-Rate CDR with Continuous-Time Linear Equalization and Deserializer
title_fullStr A 8~12Gb/s Full-Rate CDR with Continuous-Time Linear Equalization and Deserializer
title_full_unstemmed A 8~12Gb/s Full-Rate CDR with Continuous-Time Linear Equalization and Deserializer
title_sort 8~12gb/s full-rate cdr with continuous-time linear equalization and deserializer
publishDate 2018
url http://ndltd.ncl.edu.tw/handle/t3z3ky
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