Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator
碩士 === 國立中山大學 === 電機工程學系研究所 === 106 === This thesis realizes an application-specific integrated circuit (ASIC) implementation of adjustable frequency clock generator which combination of a one-bit quasi floating gate memory as reference voltage generator for the relaxation oscillator with frequency...
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| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/mb6kbm |
| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 106 === This thesis realizes an application-specific integrated circuit (ASIC) implementation of adjustable frequency clock generator which combination of a one-bit quasi floating gate memory as reference voltage generator for the relaxation oscillator with frequency divider at the output stage in TSMC 2P4M 0.35 μm CMOS technology. Quasi floating gate memory can make similar memory behavior with standard cell at a relatively low cost but the effect is compromised. Using the feature which store the data without the power of the quasi floating gate memory, the system can program an oscillator frequency by quasi floating gate memory which keeps the program state even without power but only for an hour. The clock generator can provide oscillating frequency between 462 KHz to 549 KHz. The measured power consumption is 5.1 mW during the quasi floating gate memory operates in program state and the oscillating frequency variation with VDD is about ±1.2%. The chip active area is about 0.069 mm2.
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