Acceleration strategies for SystemC kernel

• Main Authors: Ming-Siang Huang, 黃銘祥
• Other Authors: Ing-Jer Huang
• Format: Others
• Language: en_US
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/34tzdv

碩士 === 國立中山大學 === 資訊工程學系研究所 === 106 === Many manufacturers integrate several modules in the chip to enhance production efficiency in response to the increasing consumers’ needs, which elevates the complexity of chips. However, the interactions between hardware and software are more complicated because of the multi-modular construction. It takes a significant time for the simulation verification required in the early phase. It’s difficult for integrators to analyze the efficiency of the hardware and software. On the other hand, they have to consider time-to-market. The development procedure of the products can be decreased significantly if the complete simulation analysis and simulation verification to the Electronic System Level (ESL) can be conducted. Moore’s law is coming to an end, and the progress of the hardware is decreasing gradually, so we have to focus more on the software efficiency. We adopt a series of more comprehensive methods to accelerate various SystemC simulators, revise executive core, optimize date construction and optimize execution of the basic program, etc. Different from other accelerating simulation methods which target specific behavior simulators, our approach enables system developers to gain precise control of the entire system efficiently in the early period of system design and accomplish various function verifications in a limited time frame.