A Low-cost Multi-arithmetic-unit Hardware Architecture for Elliptic Curve Cryptosystem in Binary Field

碩士 === 國立中山大學 === 資訊工程學系研究所 === 106 === Since the technology has developed rapidly, the amount of data transmitted on the Internet has greatly increased. Whether money transactions or message transmission is closely related to the Internet. To protect our data from people with bad intentions, a syst...

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Bibliographic Details
Main Authors: Hung-Hsiang Chen, 陳泓翔
Other Authors: Kuang, Shiann-Rong
Format: Others
Language:zh-TW
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/d9358m
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Summary:碩士 === 國立中山大學 === 資訊工程學系研究所 === 106 === Since the technology has developed rapidly, the amount of data transmitted on the Internet has greatly increased. Whether money transactions or message transmission is closely related to the Internet. To protect our data from people with bad intentions, a system is required to deal with this problem. So the cryptography is essential. In asymmetric cryptosystem, the Elliptic Curve Cryptosystem (ECC) has the advantages of shorter key length and faster encryption/decryption speed. It is more suitable for being implemented on small electronic devices. The core operation in ECC is called point multiplication, which is calculation between point and point on curve. The operation of ECC can be divided into two parts, prime field and binary field. This thesis focuses on binary field. We use the Montgomery point multiplication algorithm under projective coordinate as the main architecture, and the high-radix Montgomery modular multiplier for multiplication operation in binary field. The Montgomery algorithm is based on addition and shifting to achieve modulo multiplication, which is easier to be implemented on hardware. It can also achieve the low-cost design because of the smaller area. We adopt the Montgomery Inversion for the inverse operation in binary field. It also uses the simple addition and shifting to implement the operation on hardware. Although its execution time is longer, the inverse operation is only needed once in overall point multiplication. So it does not have much influence on performance. The registers can be shared with other arithmetic units to further reduce the area. In this thesis, we define an Arithmetic Unit (AU) as a binary adder and a modular multiplier. The inversion operator will share the registers with the multiplier. We simulate the point multiplication operation with different number of AUs and high-radix modular multipliers. The results show that the 2AU architecture with radix-2^4 modular multiplier has the smallest area. Compared with previous designs, the area is reduced about 23% and the number of cycles is also reduced by about 26%.