| Summary: | 碩士 === 國立彰化師範大學 === 電子工程學系 === 106 === Recently, Artificial Intelligence（AI） is becoming the global technology trend. Both the industry and academic are tending to develop AI. AI is based on computing massive data at high speed and has to reduce the error rate to the minimum. Because 3D-ICs can implement high-speed data transmission and high-performance computing, they are thought to be a solution to reach the AI needs in the future. But TSVs, the critical interconnects of 3D-ICs, usually have to execute high-speed transmission with high reliability through channels with EMI, cross-talks, hot-spots, thermal variations, and all kinds of impacts. Moreover, data TSVs are usually arranged as arrays, which may cause cluster errors occur.
ECC is believed to be an effective method to improve the reliability of interconnects. Among all ECCs, one kind of one-step majority logic decodable codes, OLS codes, can correct multiple errors with high speed, but there still does not have an efficient way to construct the codes. In this thesis, a mA2DPC construction for constructing OLS codes was proposed. By the mathematical induction, we have verified that the error signals can be generated by the majority of the associated parity check bits of data bits. When the number of axes is between four and six, the mA2DPC is the optimized structure for zero-clock latency clock-level real-time high-reliability applications. To correct cluster errors, a sliding algorithm is applied. When the axis amount is m, m/2 cluster errors of size up to the height of data array can be corrected. In the error rate simulation section, a 6A2DPC is compared with a relative literature [11] and the 2DPC that our team had proposed [13]. According to the result of the simulation, we find that our work can reduce about 76.21 times of block error rate. Compared with the two pieces of literature above, the block error rate is reduced about 15.35 and 42.85 times respectively.
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