| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 106 === With the shrinking device size in deep-submicron era, the parameter shift due to process variation and aging effects has an increasing impact on the circuit yield and reliability, especially for sensitive analog circuits. If we can consider the impact of device parameter variation for the circuit performance at early design stages, it can help to significantly reduce the re-design cost and increase circuit yield. To assess the effective drift by the process variation, Monte Carlo (MC) analysis is often used. Since aging process is often a gradual change, we have to analyze the circuits repeatedly after a period of time. For modern large circuits, performing MC simulation repeatedly during aging analysis is almost infeasible due to the high complexity.
In order to improve the efficiency of aging analysis while keeping high accuracy, an incremental simulation technique is proposed in [7] based on delta circuit models. A dynamic aging sampling technique is also proposed to further reduce the number of simulations. In the literature, analog behavioral models are widely used to speed up circuit simulation. In this thesis, we try to combine delta models and behavioral models in aging analysis and develop proper behavioral models to simulate the degraded performance distribution instead of transistor-level simulation. After promoted to behavioral level, it is possible to have more improvements on the efficiency of lifetime yield analysis. As demonstrated in the experimental results, the proposed approach is indeed an effective way to improve the efficiency of lifetime yield analysis while keeping estimation accuracy.
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