A 10 Gbps Half-Rate Clock and Data Recovery with Data Independent Phase Tracking Compensation Technique

• Main Authors: Yu-Heng Cheng, 鄭宇亨
• Other Authors: Kuo-Hsing Cheng
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/rb9va4

碩士 === 國立中央大學 === 電機工程學系 === 106 === In recent years, according to the rapid development of the process and computers, the series data transmission is widely used for the bus instead of the parallel transmission and the data rate increases progressively, such as PCI-Express, SATA, USB and SONET in the fiber network. The data rate has even risen up to ten billion bits per second in the latest generation specifications. Therefore, the circuit design complexity is greatly increased. This thesis presents a clock and data recovery (CDR) with a data independent phase tracking compensation technique which takes the USB 3.1 Gen2 specification as a reference material. The proposed CDR presents a phase tracking compensation phase detector (PTCPD) which improved the drawback of the conventional bang-bang phase detector (BBPD) in high-speed transmission. When input data has long run situation, the BBPD can’t determine leading or lagging and the minimum pulse width of BBPD output signal will decrease with the increasing of data transmission rate. Above situation will degrade the jitter tolerance (JTOL) and the signal integrity. In addition, the BBPD needs re-timing circuit to integrate signal logic which is an obstacle for reducing the loop latency. The PTCPD can adjust the recovered clock phase in long run situation and use input data sampling recovered clock to remove the re-timing circuit which make JTOL enhanced. The chip is fabricated by a 90 nm standard CMOS process with a supply voltage of 1 V and the input data is 10 Gbps PRBS7 pattern. The measured jitter of the recovered clock is 3.3 psrms, 21.2 pspp, the chip area is 1.59 mm2, the core area is 0.154 mm2 and the total power consumption is 30.1 mW.