CMOS High-Frequency Circuit Design for Sensor and THz Communication Applications
碩士 === 國立中央大學 === 電機工程學系 === 106 === This thesis proposes a low-cost, high-efficiency sensor system. This design use TSMC 180-nm CMOS process because the low-Vth and use system in package technology. All of the passive device R,L,C are design on the high-substrate process GIPD(Glass Integrated Passi...
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ndltd-TW-106NCU054420122019-05-16T00:15:46Z http://ndltd.ncl.edu.tw/handle/6eyxyt CMOS High-Frequency Circuit Design for Sensor and THz Communication Applications 應用於感測器與太赫茲通訊之互補式金氧半高頻電路設計 Hsien-Chia Lin 林憲佳 碩士 國立中央大學 電機工程學系 106 This thesis proposes a low-cost, high-efficiency sensor system. This design use TSMC 180-nm CMOS process because the low-Vth and use system in package technology. All of the passive device R,L,C are design on the high-substrate process GIPD(Glass Integrated Passive Device). Use the low-metal loss to provide quality factor of the passive devices, which provides higher sensitivity and efficiency. Also this process can improve the disadvantages of the tradition process SOC(System On Chip). This thesis proposes sensor-energy harvester can provide voltage with five band 0.75、 0.9、1.8、2.18、2.4-GHz respectively, and the most efficiency can be 35% and the output voltage can be 13.5 V. This thesis proposes sensor-low power receiver uses SIP (System In Package) technology to reduce stage power consumption from the stag to stage, and the total power consumption only cost μW order cause the lower power design application, while the output can provide 2-MHz signal. This thesis proposes a low power consumption, high efficiency THz communication applications. It can be use at 200-GHz communication application by 40-nm CMOS technology. Phase Locked Loop (PLL) makes the frequency and phase stable which from 100-GHz voltage control oscillator (VCO) generates at input signal. And supply to next stage-Buffer & Amplifier when the input signal be locked. When signal is grew up enough for power amplifier (PA) to use. Signal gets more higher output power by power amplifier. The high-power input signal will be raised up from 100-GHz to 200-GHz by the frequency Doubler (2X), and it can be modulate from ASK mod. Finally the output single will be control at 20-Gb/s digital data which at 200-GHz to the next stage high-gain antenna, and the total output power can be -0.6dBm. Chun-Hsing Li 李俊興 2017 學位論文 ; thesis 113 en_US |
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碩士 === 國立中央大學 === 電機工程學系 === 106 === This thesis proposes a low-cost, high-efficiency sensor system. This design use TSMC 180-nm CMOS process because the low-Vth and use system in package technology. All of the passive device R,L,C are design on the high-substrate process GIPD(Glass Integrated Passive Device). Use the low-metal loss to provide quality factor of the passive devices, which provides higher sensitivity and efficiency. Also this process can improve the disadvantages of the tradition process SOC(System On Chip).
This thesis proposes sensor-energy harvester can provide voltage with five band 0.75、 0.9、1.8、2.18、2.4-GHz respectively, and the most efficiency can be 35% and the output voltage can be 13.5 V. This thesis proposes sensor-low power receiver uses SIP (System In Package) technology to reduce stage power consumption from the stag to stage, and the total power consumption only cost μW order cause the lower power design application, while the output can provide 2-MHz signal.
This thesis proposes a low power consumption, high efficiency THz communication applications. It can be use at 200-GHz communication application by 40-nm CMOS technology. Phase Locked Loop (PLL) makes the frequency and phase stable which from 100-GHz voltage control oscillator (VCO) generates at input signal. And supply to next stage-Buffer & Amplifier when the input signal be locked. When signal is grew up enough for power amplifier (PA) to use. Signal gets more higher output power by power amplifier. The high-power input signal will be raised up from 100-GHz to 200-GHz by the frequency Doubler (2X), and it can be modulate from ASK mod. Finally the output single will be control at 20-Gb/s digital data which at 200-GHz to the next stage high-gain antenna, and the total output power can be -0.6dBm.
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author2 |
Chun-Hsing Li |
author_facet |
Chun-Hsing Li Hsien-Chia Lin 林憲佳 |
author |
Hsien-Chia Lin 林憲佳 |
spellingShingle |
Hsien-Chia Lin 林憲佳 CMOS High-Frequency Circuit Design for Sensor and THz Communication Applications |
author_sort |
Hsien-Chia Lin |
title |
CMOS High-Frequency Circuit Design for Sensor and THz Communication Applications |
title_short |
CMOS High-Frequency Circuit Design for Sensor and THz Communication Applications |
title_full |
CMOS High-Frequency Circuit Design for Sensor and THz Communication Applications |
title_fullStr |
CMOS High-Frequency Circuit Design for Sensor and THz Communication Applications |
title_full_unstemmed |
CMOS High-Frequency Circuit Design for Sensor and THz Communication Applications |
title_sort |
cmos high-frequency circuit design for sensor and thz communication applications |
publishDate |
2017 |
url |
http://ndltd.ncl.edu.tw/handle/6eyxyt |
work_keys_str_mv |
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