| Summary: | 碩士 === 國立交通大學 === 電控工程研究所 === 106 === Owing to new technological advances, the central processor unit (CPU) used in mobile devices needs faster logic computing capability, higher reliability, and higher stability. In order to make the CPU operate in a stable environment, the power supply of the CPU requires high efficiency and low power consumption. Therefore, dynamic voltage identification (DVID) technique and adaptive voltage position (AVP) technique are usually implemented in the voltage regulator module (VRM) for the CPU. In addition, in conventional design, multiple DC-DC buck converters are used to provide multi-output voltage for the multi-cores of the CPU. However, this architecture is not suitable for the CPU because of the cost and area consideration. Consequently, a single inductor multi-output (SIMO) DC-DC converter becomes a good candidate due to the advantage of compact size and low cost. However, SIMO converter has larger output ripple and poor load variation response, which are not allowed by the CPU. As the result, each output of the SIMO converter needs to cascade a linear regulator to lower the output voltage ripple. However, due to the wide load range of CPU, the analog low-dropout (A-LDO) regulator requires larger dropout voltage, which degrades system power conversion efficiency. Therefore, the proposed VRM includes the SIMO converter and cascaded digital low-dropout (D-LDO) regulators which have low dropout voltage characteristic and thus lower the voltage ripple without degrading power conversion efficiency. Besides, the proposed VRM integrates AVP and DVID techniques as auto calibration dual-AVP (ACD-AVP) technique with the help of the D-LDO, thereby improving overall performance of the VRM under any load condition and OPPs.
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