| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 106 === This thesis consists of two parts, including eliminating the intermodulation distortion to enhance the linearity of a 2.4 GHz dual-mode power amplifier and realizing a Watt-Level high-efficiency 2.45 GHz stacked power amplifier with a fully integrated design.
In the first part, a 2.4 GHz dual-mode power amplifier which improves the efficiency at low-power region by the physical-size reduction method using TSMC 0.18-μm SiGe BiCMOS process is presented; moreover, the linearity is enhanced by utilizing a quarter-wave length bias implemented on a PCB FR-4 to eliminate the intermodulation distortion.
In the second part, a Watt-Level high-efficiency 2.45 GHz stacked power amplifier is demonstrated using TSMC 0.18-μm SiGe BiCMOS process. The stacked structure is used to increase the optimized output impedance, hence achieving the goals of high-efficiency, high-linearity, and high-integrated level as well.
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