| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 106 === As rapid development of hardware technique, many neural networks (NNs) accelerators have been proposed. However, convolution neural networks (CNNs) needs a lot of calculation and a large amount of data access and movement, the energy cost on the data access may even exceed the computation consumption. Therefore, how to
manage data reuse efficiently and reduce data access has turned into a research theme. In this thesis, we propose a three-dimensional (3-D) Network-on-Chip (NoC) with vertical 3D stacked memory, using fused-layer technique to reduce large memory footprint. First, we realize a fusion-based 3D NoC that makes data reuse effectively to decrease data access with DRAM, and transferring data through routers can improve drawbacks of traditional Bus. Meanwhile, transmitting data with TSVs can further decrease the energy consumption. We also propose a high efficient data flow with pipelined optimization which can process more data parallel. Moreover, adding dynamic voltage/frequency scaling (DVFS) and Prefetch technique into vault controller to better system efficacy. Finally, we construct latency and power model to analyze performance. Overall, total energy of fusion-based 3D NoC reduces 61.9% and system efficiency rises 2.6× with conventional 3D baseline architecture. With different DRAM, the energy of fusion-based 3D NoC with WIDEIO2 drops 95.5% and system efficiency increases 32.6× comparing to conventional NoC with 2D baseline DDR3.
|
|---|
