| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 106 === Reed-solomon (RS) code and BCH code are popular error control code (ECC) applied on communication system and storage device. Using soft-decision decoding can
improve the error correct ability over the same code length and code rate. However the algorithm is more complex and hard to implement. When code length extends, the cost of the hardware and algorithm complexity increase nonlinearly. In this thesis, we refer a new
type of soft-decision decoding algorithm. This algorithm combines numbers of RS/BCH codewords and transforms to Low-density-parity-check (LDPC) codeword through simple
mathematical methods. Using LDPC code, is also a popular ECC with soft-decision decoding, to decode RS/BCH code can improve the performance without changing the
code length and code rate.
At last, we propose a (71,64) RS code overGF(2^9), corresponding to (46647,42102) LDPC code, the code rate both are 0.9. Based on the special LDPC code structure, we design a pipeline LDPC decoder. The RS decoder with iterative soft decision decoding contains two LDPC pipeline decoders and other computing units for transformation. We implement the RS decoder in 65nm CMOS process at synthesis state. This hardware occupying 4.66mm2 area can achieve a throughput of 6.82Gbps under clock frequency of 300MHz.
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